Recently, with the progress of semiconductor manufacturing techniques and with the expansion of the application of semiconductor, a memory devices of large capacities are developed and promoted. Particularly, DRAM (Dynamic Random Access Memory) having the advantage of very-large-scale integration (VLSI) by combining into one memory cell one capacitor and one transistor has been considerably developed.
This type of DRAM applies the 4M DRAM by arranging the three dimensional structure having a stack type capacitor cell and a trench type capacitor cell instead of a prior planar type capacitor cell in the memory cell structure, but becomes difficult to apply to a 16M DRAM. Also, in the above stack type capacitor cell, step coverage problems occur owing to the capacitor structure stacked on the transistor, and in the trench type capacitor cell, leakage current problems between trenches occur during the scale down process. As the result, this type of DRAM is difficult to apply to a 64M DRAM.
Therefore, to sole the problem of this large capacity DRAM, a stack-trench combined type capacitor as a new three dimensional structure has been proposed, which is shown in FIG. 1.
Referring to FIG. 1 wherein a conventional stack-trench combined type capacitor is shown, an active region is defined by growing a field oxide layer 101 on the semiconductor substrate 100 and a first conductive layer such as an impurity-doped first polycrystalline silicon layer, namely, gate electrode 2, is formed on the active region by interpositing the gate oxide layer 1, and then, a first conductive layer 5, e.g., an impurity-doped first polycrystalline silicon layer, is formed on the field oxide layer 101 in such a manner that the first conductive layer is connected with a gate electrode of an adjacent memory cell. Thereafter, a source region 3 and a drain region 4 are formed on the semiconductor substrate surface of both sides of the gate electrode 2, and a first insulating layer 6 is formed on the entire surface of the structure as described above.
Through the application of a mask on the first insulating layer 6 and between the field oxide layer 101 and the gate electrode 2, a trench is formed in the semiconductor substrate 100, and then, a first electrode pattern which is formed by a second conductive layer 12b, e.g., an impurity-doped second polycrystalline silicon layer, is formed on both the inside of the trench 10 and the first insulating layer 6. Here, the second conductive layer 12b is used as a first electrode of the capacitor. Then, a dielectric film 14 covering the surface of the first electrode pattern is formed, and then, a third conductive layer 15, e.g., an impurity-doped third polycrystalline silicon layer is formed on the entire surface of the above described structure, so that the third conductive layer 15 is used as a second electrode of the capacitor, thereby forming the stack-trench combined type capacitor.
Since the prior stack-trench combined type capacitor descried above in detail as shown in FIG. 1 directly forms the second conductive layer used as the first electrode of the capacitor on the inside of the trench, the surface area of the trench gets small. When the capacitor is formed by forming the dielectric film and the third conductive layer on the small surface, i.e., the surface of the trench in turn, the problem of capacitance loss arises.